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HDLC
The following figure represents the AC timing from Table 29 . Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
TDM/SICLK (Input)
Input Signals:
t SEIVKH
t SEIXKH
TDM/SI
(See Note)
t SEKHOV
Output Signals:
TDM/SI
(See Note)
t SEKHOX
Note: The clock edge is selectable on TDM/SI.
Figure 21. TDM/SI AC timing (external clock) diagram
10 HDLC
This section describes the DC and AC electrical specifications for the high level data link control (HDLC),
of the MPC8309.
10.1
HDLC DC electrical characteristics
The following table provides the DC electrical characteristics for the MPC8309 HDLC protocol.
Table 30. HDLC DC electrical characteristics
Characteristic
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input current
Symbol
V OH
V OL
V IH
V IL
I IN
Condition
I OH = –2.0 mA
I OL = 3.2 mA
—
—
0 V ≤ V IN ≤ OV DD
Min
2.4
—
2.0
–0.3
—
Max
—
0.5
OV DD + 0.3
0.8
±5
Unit
V
V
V
V
μ A
10.2
HDLC AC timing specifications
The following table provides the input and output AC timing specifications for HDLC protocol.
Table 31. HDLC AC timing specifications 1
Characteristic
Outputs—Internal clock delay
Outputs—External clock delay
Outputs—Internal clock high impedance
Symbol 2
t HIKHOV
t HEKHOV
t HIKHOX
Min
0
1
0
Max
9
12
5.5
Unit
ns
ns
ns
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
32
Freescale Semiconductor
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